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4-BIT MCU FOR REMOTE CONTROLLER(MASK TYPE)
DESCRIPTION
SC73C1602 is one of Silan' 4-bit CMOS single-chip micro-controllers s for infrared remote control transmitters (IRCTs). It can be implemented in various IRCTs circuits by mask option.
SOP-16-225-1.27
FEATURES
* Wide operating voltage (1.8~4.0V) * Low static power consumption (<1mA) * ROM: 2K x 9 bits * Data memory: 32 x 4bits * Timer/counter: (10~15 bits) * 8-bit timer, generates various frequencies and duty carrier * 16 I/O pins, four 4-bit I/O ports (export P53) * Oscillator frequency (fosc): fosc=4MHz (TYP.) or fosc=455KHz(TYP.) * Operating frequency (fmain): fosc/8 (fosc=4MHz) fosc (fosc=455KHz) * Instruction cycle: 5/fmain * Support low voltage detection
SSOP-20-300-0.65 SSOP-20-225-0.65 SOP-20-300-1.27 SOP-20-375-1.27
APPLICATIONS
* Infrared remote control devices, such as TV, Video Cassette Recorder, VTR, laser phonograph and acoustics remote controllers.
ORDERING INFORMATION
Part No. SC73C1602N-XXX SC73C1602N-XXXG SC73C1602N-XXXTR SC73C1602N-XXXGTR SC73C1602NA-XXX SC73C1602NA-XXXG SC73C1602NA-XXXTR SC73C1602NA-XXXGTR SC73C1602NC-XXX
Package SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27 SSOP-20-225-0.65
Pin Layout Format
Material Pb free Halogen free Pb free Halogen free
Package Type Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube
Format 1
Pb free Halogen free Pb free Halogen free Pb free
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Part No. SC73C1602NC-XXXG SC73C1602NC-XXXTR SC73C1602NC-XXXGTR SC73C1602ND-XXX SC73C1602ND-XXXG SC73C1602ND-XXXTR SC73C1602ND-XXXGTR SC73C1602NE-XXX SC73C1602NE-XXXG SC73C1602NE-XXXTR SC73C1602NE-XXXGTR SC73C1602M-XXX SC73C1602M-XXXG SC73C1602M-XXXTR SC73C1602M-XXXGTR SC73C1602MA-XXX SC73C1602MA-XXXG SC73C1602MA-XXXTR SC73C1602MA-XXXGTR SC73C1602MC-XXX SC73C1602MC-XXXG SC73C1602MC-XXXTR SC73C1602MC-XXXGTR SC73C1602MD-XXX SC73C1602MD-XXXG SC73C1602MD-XXXTR SC73C1602MD-XXXGTR SC73C1602ME-XXX SC73C1602ME-XXXG SC73C1602ME-XXXTR SC73C1602ME-XXXGTR SC73C1602Q-XXX SC73C1602Q-XXXG SC73C1602Q-XXXTR SC73C1602Q-XXXGTR SC73C1602QA-XXX SC73C1602QA-XXXG SC73C1602QA-XXXTR SC73C1602QA-XXXGTR
Package SSOP-20-225-0.65 SSOP-20-225-0.65 SSOP-20-225-0.65 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27 SSOP-20-225-0.65 SSOP-20-225-0.65 SSOP-20-225-0.65 SSOP-20-225-0.65 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SOP-16-225-1.27 SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SSOP-20-300-0.65 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27 SOP-20-300-1.27
Pin Layout Format
Material Halogen free Pb free Halogen free Pb free Halogen free
Package Type Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel
Format 1
Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free
Format 2
Format 3
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Part No. SC73C1602QC-XXX SC73C1602QC-XXXG SC73C1602QC-XXXTR SC73C1602QC-XXXGTR SC73C1602QD-XXX SC73C1602QD-XXXG SC73C1602QD-XXXTR SC73C1602QD-XXXGTR
Package SSOP-20-225-0.65 SSOP-20-225-0.65 SSOP-20-225-0.65 SSOP-20-225-0.65 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27 SOP-20-375-1.27
Pin Layout Format
Material Pb free Halogen free Pb free Halogen free Pb free Halogen free Pb free Halogen free
Package Type Tube Tube Tape & Reel Tape & Reel Tube Tube Tape & Reel Tape & Reel
Format 3
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS (Tamb=25C)
Characteristics Supply Voltage Input Voltage Output Current Power Consumption Storage Temperature Operating Temperature Symbol VDD VIN IOUT (P53) PD Tstg Topr Value -0.3 ~ +5.0 -0.3~VDD+0.3 -12.0 500 -40~+125 -20~+75 Units V V mA mW C C
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ELECTRICAL CHARACTERISTICS (Tamb=25C, VDD=3.0V)
Characteristics Power Supply Voltage Low Voltage Reset Voltage Operating Current Oscillation Frequency Static Power Consumption Symbol VDD VLVD IDD FOSC IDS Test Conditions All function All function In operating MASK1 MASK2 Oscillator stops P00-P03 Input Pull-Down Resistor R VDD=3V P10-P13 P20-P23 P50-P52 High Input Voltage Low Input Voltage VIH VIL --P53 High Output Current IOH VDD=3V VOH=2.7V P00-P03 P10-P13 P20-P23 P50-P52 P53 Low Output Current IOL VDD=3V VOL=0.3V P00-P03 P10-P13 P20-P23 P50-P52 -0.15 -mA -1.0 ---2.0 -mA 0.7VDD 0 ----12.0 VDD 0.3VDD -V V 80 95 110 KW Min. 1.8 1.1 -300K 2M -Typ. 3.0 --455k 4M -Max. 4 1.4 0.5 2M 6M 1 Units. V V mA Hz Hz mA
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PIN CONFIGURATIONS (20 PINS CONFIGURATION)
SOP-20/SSOP-20 Pin Layout Format 1 SOP-20/SSOP-20 Pin Layout Format 2
SOP-16 Pin Layout Format 2
SOP-20/SSOP-20 Pin Layout Format 3
GND P50 P51 XT1 XT2 P52 P00 P01
1 2 3 4 5 6 7 8
16 VDD 15 P53
SC73C1602
14 P23 13 P22 12 P21 11 P20 10 P13 9 P12
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PIN DESCRIPTION
Symbol VDD GND RSTN XT1 XT2 P00~P03 P10~P13 P20~P23 P50-P52 P53 Power Supply positive Power Supply negative Reset pin (active low) OSC output pin OSC input pin 4-bit I/O pin. In input mode, it is used as the keyboard-scan input port (with internal pull-down resistor). In output mode, it is used as the keyboard-scan output port. Same as P00-P03 Same as P00-P03 Same as P00-P03 Outputs remote control signal with carrier. Description
Note: The package of the IC is to be determined by customer.
PORT BLOCK DIAGRAMS
Port data Pin OUTPUT I/O control
Port detection
PIN_DECT Port read data bus
INPUT
key-on wakeup input
P0, P1, P2, P50, P51, P52 Configuration
Carrier rectify Carrier Register PORT P53 Voltage drop detection control at operating Port P53
Carrier close
P53 configuration Note: The I/O mode of P0, P1, P2 , P5 port refer to the PR register.
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FUNCTION DESCRIPTION
1. PC PC refers to the program counter, 11 bits. The maximum addressing area is 2K ROM .The program counter contains the address of the instruction that will be executed next. The PC value is cleared to 0 after reset. The PC is set to predefined value when one of the 3 following occasions occurs: 1) when the JUMP instruction is executed; 2) when a subroutine call is back; 3) when a program call is back. In the SC73C1602, all instructions are one-byte OP Code instructions, so generally PC increments by 1 each time an instruction is executed. 2. MBR Memory buffer register (MBR) is the write-only, higher 4-bit of the program pointer. The ROM of SC73C1602 can be divided into 16 blocks. Each block has 128 bytes. These blocks can be addressed by the MBR. When the program starts executing a branch instruction, it must load the corresponding value to the MBR register, and then executes the command BSS label. 3. STACK Stack register stores the previous value of program pointer during execution of subroutine calls, 11 bits. Because there is two-level hardware stack registers, two-level programs can be called. When the user tries to make a nested two-level program call, an error will occur. 4. B, H, D Lower 3-bit of register B and all bits (4-bit) of H, D (ROM address is formed according to BHD order) are used as pointers pointing to data table when accessing data in ROM whose space of 2K can be used for data table, otherwise, register H, D act as general purpose register as others. Data lookup in ROM automatically whose 11bit address is decided by lower 3-bit of register B and all bits of register H & D, is available through corresponding instructions. 5. ROM Address 000H 001H 002H Subroutine call start address 01FH 020H Program address or 7FFH Table data 2K x 9 bits
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6. CH0, CH1, CL0, CL1 CH0, CH1, CL0 and CL1 are carrier level control registers for controlling the high and low level to /fosc and CL 1 /fosc. 7. LL, LH LL register, 4 bits, LH register, 1 bit. LH[0]LL[3:0] is the address pointer of RAM. 8. RAM Data memory consists of 32x4 bits and is used to store temporary data and results after a program is executed. It can address the entire RAM areas by the pointer LH[0]LL[3:0]. When reset, the contents of RAM are not defined. We recommend users to initialize it at the beginning of their software program. 9. ALU The arithmetic and logic unit plays a leading role in performing various operations of 4-bit binaries. The operation of ALU will change the carry flag (CF) and the zero flag (ZF). 10.Acc 4-bit accumulator, it is mostly used to store data and results. 11.CF Carry flag. 12.SF Status flag bit, the value of SF is 1 after reset. 13.PR (PR , PR2) The port mode register, which specifies the input mode or output mode of the I/O port, is 4-bit write-only. When PR=1, the corresponding port is set to output mode. PR=0, it is set to input mode. The execution of the HOLD instruction won'affect the I/O modes of operation. When reset, PR=0. The port is in input mode. t
PR.3 PR.2 PR.1 PR.0 P0 mode select P10, P11 mode select P12, P13 mode select P2 mode select
-PR2.2 PR2.1 PR2.0 P50 mode select P51 mode select P52 mode select
CH 1
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14.PORT SC73C1602 has 4 groups of I/O ports, totally 16 pins. Each group can operate in both input and output mode (except P53). Details are as follows: P0 port: P00-P03, 4-bit input/output port. The PR1.0 determines the port operation mode. In input mode, it has an internal pull-down resistor and can be used for keyboard scan input. When the input level is high, it can release the HOLD mode. In output mode, it can be used for keyboard scan output. P1 port: P10-P13, same as P0 port, PR1.1 determines the port operation mode. P2 port: P20-P23, same as P0 port, PR1.2 determines the port operation mode. P5 port: P50-P52, same as P0 port. P53: large current output port, this pin is used to output infrared remote signal. If P53 is set to 1, this pin outputs modulated signal with carrier. If it is set to 0, it outputs low level voltage. 15. Timer/counter SC73C1602 has two internal timers: One is a 17-bit timer. The clock source of the timer is main frequency (fmain) of the circuit. There are timing steps from 10 (which generates pulses with frequency fmain/2 10) to 15 (fmain/215). The timer can output pulse frequency ranging from fmain/210 to fmain/215, and can be used for timer after releasing the HOLD mode. It can also be used as a WDT. After the HOLD mode released and the timer reset instruction TMRST executed, the timer value is cleared. The other timer is a carrier generator. Setting different length of high and low level time span respectively through programming, it generates various different duty and frequency carriers. 16. TR Timer register, it selects the status of the timer mode, 4-bit write-only. SC73C1602 has no special instructions to read the register, so it uses the following instructions: LD A, TM or LD @LL, TM.
3 IBNS 2 1 TIBS TR timer register 0
17. IBNS The control bit of the read timer. When the value is 0, it reads TM3 (IT3), and IT2~IT0 become 0. When the value is 1, it reads 4-bit data TM3~TM0(IT3~IT0). TM3: 215/fmain TM2: 214/fmain TM1: 213/fmain TM0: 212/fmain Example: when the crystal oscillator select 455KHz, the corresponding time of port P50 is 2 /455 9ms. This means the time from TM=1111B to 1101 is 9ms, and the time from TM=1111B to 1110 is 4.5ms.See the following program: LD LD TMRST A#1000B TM,A
12
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...... LD LD LOOP: LD XOR JMPS END In above program, the time from TMRST start to END is 4.5ms, that it from TM=1111B to 1110B is 4.5ms.. Time change :
4.5ms 9ms
L,#TEMP @LL,#1110B A,TM A,@LL LOOP
9ms 9ms 18ms 36ms 18ms 36ms
The maximum adjustable time of the timer is 216/fmain. When the timer acts as a WDT and the timer is activated, it must execute the TMRST instruction and clear the timer in 216/fmain' time, otherwise, it will lead the WDT to s overflow, and causes the MCU to reset. 18. LVD Circuit The LVD circuit monitors the power supply voltage and applies an internal reset to the micro-controller. The LVD circuit has the following functions: *Generates an internal reset signal when VDD VLVD note 1 . *Cancels an internal reset signal when VDD > VLVD. Where, VDD: power supply voltage. VLVD: LVD detection voltage.
Notes. 1. Actually, there is a short oscillation stabilization wait time before the circuit is in operation mode. The oscillation stabilization wait time is about 216/fmain. 2. The LVD circuit generates an internal reset signal when the power supply voltage has fallen. When the circuit is sending code, it will cause a large current. When using old batteries (high resistor), battery output voltage will drop. When the output voltage is lower than a reference value, the
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oscillator will stop. This causes system to malfunction. In this condition, the system will initiate the LVD circuit to generate an internal reset signal to remove the malfunction. 19.Instruction Cycle Instructions and internal operations are executed in synchronization with the main clock. The minimum unit of instruction is called the instruction cycle. SC73C1602 has 1 and 2-cycle OP Code instructions. An instruction cycle consists of 5 states (STCLK1 - STCLK5). Each state consists of 1 main clock. Therefore, the instruction cycle time is 5/fmain [s]. 20.The Carrier 1. 2. fcarry is the output carrier frequency. Fin is the input frequency of the carrier generator (a register concerned with the settings of the carrier). It is also the oscillation frequency of the IC. fcarry = Fin / ( CH+CL+2 ). For example, 38.10(105) at Fin =4000KHz, 38.10 mean the carrier frequency that can be achieved under certain conditions, If CH + CL + 2 = 105, the generated carrier frequency is 38.10KHz. 3. 4. CH: the register that determines the duration of the high level carrier, the duration of the high level carrier is: (CH + 1 ) / Fin . CL: the register that determines the duration of the low level carrier, the duration of the low level carrier is : ( CL + 1 ) / Fin .
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INSTRUCTION SETS
1. Transmit instruction Instruction LD A, LL LD A, LH LD A, B LD A, H LD A, D LD A, @LL LD A, #k LD CL1, A LD CL0, A LD CH1, A LD CH0, A LDH A, @BD LDL A, @BD LDS A, @BD LDH @LL, @BD LDL @LL, @BD LDS @LL, @BD LD LL, A LD LH, A LD LL, #k LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD PR, A LD PR2, A LD TM, A LD A, TM 1. 2. 3. 4. 5. 6. 7. 8. LD A, LL LD A, LH LD A, D LD A, H LD A, B LD A, @LL LD A, #k LDL A, @BD A LL A LH AB AH AD A RAM(LL) Ak CL1 A CL0 A CH1 A CH0 A A ROM(BD)7-4 A ROM(BD)3-0 A ROM(BD)8 RAM(LL) ROM(BD)7-4 RAM(LL) ROM(BD)3-0 RAM(LL) ROM(BD)8 LL A LH A LL k RAM(LL) A RAM(LL) k DA HA BA PR A PR2 A TM A A TM Load values in the LL register to the accumulator. Load values in the LH register to the accumulator. Load values in the D register to the accumulator. Load values in the H register to the accumulator. Load values in the B register to the accumulator. Load the contents of RAM pointed at by the LL ( LL & LH) register to accumulator. Load the 4 bit immediate K to accumulator. Load the lower 4 bit of ROM data pointed at by the BHD to accumulator. Operation CF ----------------------------------------------------------SF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycle 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2 2 2 2 2 2
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9. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
LDH A, @BD LDS A, @BD LDL @LL, @BD LDH @LL, @BD LDS @LL, @BD LD LL, A LD LH, A LD LL,#K LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD CL1, A LD CL0, A LD CH1, A LD CH0, A LD PR, A LD PR2, A LD TM, A LD A, TM
Load the higher 4 bit of ROM data pointed at by the BHD to accumulator. Load the highest 1 bit of ROM data pointed at by the BHD to accumulator Load the lower 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the higher 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the highest 1 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Load the contents of the accumulator to the LL register. Load the contents of the accumulator to the LH register. Load immediate K to the LL register. Load the content of the accumulator to the RAM pointed at by the LL register. Load the immediate K to RAM pointed at by the LL register. Load the content of the accumulator to the D register. Load the content of the accumulator to the H register. Load the content of the accumulator to the B register. Load the content of the accumulator to the CL1 register. Load the content of the accumulator to the CL0 register. Load the content of the accumulator to the CH1 register. Load the content of the accumulator to the CH0 register. Load the content of the accumulator to the port register(PR). Load the content of the accumulator to the port register(PR2). Load the content of the accumulator to the timer register. Load the content of the timer register to the accumulator.
Execution the above transmit instructions will not affect the carry flag, and the status flag remains 1. 2. Input/output instructions Instruction LD A, %p LD @LL, %p LD %p, A LD %p, @LL a. b. c. d. LD A, %P LD @LL, %p LD %p, A LD %p, @LL Operation A PORT(p) RAM(LL) PORT(p) PORT(p) A PORT(p) RAM(LL) Move the value of port(P) to the accumulator Move the value of port(P) to RAM pointed at by the LL register. Move the contents of the accumulator to port (P). Load the contents of RAM pointed at by the LL register to port(P). CF --------SF /Z /Z 1 1 Cycle 2 2 2 2
The above four input/output instructions are used mostly for port operation, the two read instructions will affect the status flag SF.
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3. Arithmetic and logical instructions Instruction ADD A, @LL ADDC A, @LL ADD A, #k ADD LL, #k SUBRC A, @LL INC @LL DEC @LL INC LL INC LH DEC LL DEC LH INC D INC H INC B DEC D DEC H DEC B AND A, @LL OR A, @LL XOR A, @LL Operation A A+RAM(LL) A A+RAM(LL)+CF A A+k LL LL+k A RAM(LL)-A-/CF RAM(LL) RAM(LL)+1 RAM(LL) RAM(LL)-1 LL LL+1 LH LH+1 LL LL-1 LH LH-1 D D+1 H H+1 B B+1 D D-1 H H-1 B B-1 A A&RAM(LL) A A | RAM(LL) A A^RAM(LL) CF --C ----C ------------------------------SF /C /C /C /C C /C C /C /C C C /C /C /C C C C /Z /Z /Z Cycle 1 1 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1
1. 2. 3. 4.
ADD A, @LL ADDC A, @LL ADD A,#K ADD L,#K
Add the contents of RAM pointed at by the LL to accumulator, store the sum in the ACC. This operation will affect SF, SF=/CF. Add the contents of RAM pointed at by the LL register to accumulator with carry. Store the carry bit in the CF. This operation will affect SF, SF=/CF. Add immediate K to accumulator. Store the sum in the ACC. This will affect SF, SF=/CF. Add immediate K to the LL register. Store the sum in the LL. This will affect SF, SF=/CF. Subtract instruction with borrow(the complement of carry). Subtract the contents of the accumulator from the contents of RAM pointed at by the LL register, subtract the complement of the carry bit, then store the results in the accumulator, transfer the carry bit to the CF, this will affect SF and CF, SF=CF. Increment instruction. Increment the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=/CF. Decrement instruction. Decrement the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=CF. Increment instruction. Increment the contents of the D register by 1. This will affect SF, SF=/CF. Increment instruction. Increment the contents of the H register by 1. This will affect SF, SF=/CF.
5.
SUBRC A, @LL
6. 7. 8. 9.
INC @LL DEC @LL INC D INC H
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10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
INC B DEC D DEC H DEC B INC LL INC LH DEC LL DEC LH AND A, @LL OR A, @LL XOR A,@LL
Increment instruction. Increment the contents of the B register by 1. This will affect SF, SF=/CF. Decrement instruction. Decrement the contents of the D register by 1. This will affect SF, SF=CF. Decrement instruction. Decrement the contents of the H register by 1. This will affect SF, SF=CF. Decrement instruction. Decrement the contents of the B register by 1. This will affect SF, SF=CF. Increment instruction. Increment the contents of the LL register by 1. This will affect SF, SF=/CF. Increment instruction. Increment the contents of the LH register by 1. This will affect SF, SF=/CF. Subtract 1 from the content in register LL. SF is affected, SF=/CF. Subtract 1 from the content in register LH. SF is affected, SF=/CF. The contents of the accumulator and RAM pointed at by the LL register are ANDed and the results are stored in the accumulator. SF changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are ORed and the results are stored in the accumulator. SF changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are XORed and the results are stored in the accumulator. SF changed, SF=/Z.
4. Bit operation instructions Instruction CLR @LL, b SET @LL, b TEST @LL, b a. b. c. CLR @LL, b SET @LL, b TEST @LL, b Operation RAM(LL)b0 RAM(LL)b1 SF/RAM(LL)b CF ------SF 1 1 * Cycle 2 2 2
Clear the B-bit of the RAM pointed at by the LL register. Set the B-bit of the RAM pointed at by the LL register to be 1. Test the B-bit of the RAM pointed at by the LL register. If this bit is1, the SF is set to 0; otherwise, the SF is set to 1.
5. Carry operation instructions Instruction CLR CF SET CF TESTP CF a. b. c. CLR CF SET CF TESTP CF CF0 CF1 SFCF Clear the carry flag to logic zero. Set the carry flag to logic 1. Test the carry flag, send the carry flag to SF. Operation CF 0 1 --SF 1 1 * Cycle 2 2 1
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6. Branch instructions Instruction BSS label JMPS label instruction Set for details. BSS label Jump to destination address label with range of 128 bytes JMPS label Jump to destination address label with range of 2K program. Symbol description of above instructions: a. b. c. d. label #k b %p Destination address of jump Immediate (0~15) Bit addressing (0~3) Port address Operation CF ----SF 1 1 Cycle 2 3
Jump instruction is active only when SF is 1, or else next instruction is executed. Please read the Pseudo-
7. Subroutine instructions Instruction CALLS label RET 01FH. 8. Other instructions Instruction HOLD NOP TMRST a. b. c. HOLD NOP TMRST Reset timer counter Operation CF ------SF 1 ----Cycle 1 1 1 Operation CF ----SF ----Cycle 2 2
When executing subroutine call and return instructions, the subroutine starting address is limited from 000H to
After executing this instruction, MCU is in the power-save mode, the clock stops oscillation and power consumption reduces dramatically. Null operation. It doesn' affect anything. t Timer clear command. It will clear all values of the timer to 0. This instruction is often used to reset WDT in program.
9. Pseudoinstruction ORG Format: [Label:] ORG address Function: Redefine following start address Expression: Label: selectable Address: redefined address, can be binary, decimal or hexadecimal. Redefined address is an absolute address which could not be returned back. That is, the redefined address
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should be higher than that above, or a fault is occurred during compiling. 000H is defaulted if no address is set by ORG instruction. Example: ORG 0100H EQU Format: Symbol EQU digital Function: Define a digital as a symbol. Symbol Expression: Symbol should be legal, and digital should be binary, decimal or hexadecimal. There is no colone before EQU in definition, and it can only useful after the definition. Example: Data1 EQU 12H Data2 EQU 1001B DB Format: [Label:] [num] DB data Function: Define data with number of num. Expression: Label: selectable Num: indicates number of data, default value is 1. Data: data to be written to ROM. It should smaller than 0X200 as ROM is only 9-bit.lower 9-bit value of data is taken with warning if it is more than 0x200.( only lower 8-bit is taken if the instruction is used for data table) Example: DB 12H ; Define one data ; Define one data DB 10010B digital.
12H DB 55H ; Define continuous 18 data JMPS Format: [Label:] JMPS address Function: Jump in ROM. Expression: Label: selectable Address can be a digital, symbol defined by EQU or the address symbol. Combined by: LD MBR, #k BSS label
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The instruction is 2-byte long, and it can jump to any position in the ROM. Example: JMPS MAIN JMPS 100H VENT Format: VENT label Function: Define the entry and reset address of sub-program. Expression: Label is the sub-program name or the address symbol. Use VENT to specify the entry and reset address of the sub-program, and it must be at the beginning of the program. The first VENT denotes the reset address and the following VENT instructions denote the entry of the sub-program. In general, 16 sub-programs can be defined at most. All the sub-programs called by CALL instruction should be defined in VENT, or else errors will occur in assembly. Example: VENT MAIN VENT SUB1 VENT SUB2 ... ... ... ... .. ORG 100H MAIN: NOP NOP CALLS SUB1 CALLS SUB2 ............. SUB1: ............. SUB2: ............. END Format: END Function: Use the END instruction to end the assembly of a program. Expression: END pseudoinstruction ends the assembly of a program and the content after END will not be processed by assembler. If END is omitted, the assembler will process all the lines of the source file. Example: END
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TYPICAL APPLICATION CIRCUIT (I) - REFER PIN LAYOUT FORMAT 1
VDD VDD 270
47 F 0.1 F
2 1 2 3 C1 33pF 4 4MHz 5 C2 33pF 6 7 8 9 P52 P00 P01 P02 XT2 XT1 P22 17 P21 16 P20 15 P13 14 P12 13 P11 12 P10 11 GND P50 P51 VDD 20 P53 19 P23 18 K8 K7 K6 K5 K4 K3 K2 K1 K57 K16 K15 K14 K13 K12 K11 K10 K9 K58 K24 K23 K22 K21 K20 K19 K18 K17 K59 K32 K31 K30 K29 K28 K27 K26 K25 K60 K40 K39 K38 K37 K36 K35 K34 K33 K61 K48 K47 K46 K45 K44 K43 K42 K41 K62 K56 K55 K54 K53 K52 K51 K50 K49 K63 VDD
SC73C1602
10 P03
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TYPICAL APPLICATION CIRCUIT (II) - REFER PIN LAYOUT FORMAT 2
TYPICAL APPLICATION CIRCUIT (III) - REFER PIN LAYOUT FORMAT 3
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PACKAGE OUTLINE
SOP-16-225-1.27 Unit:mm
SOP-20-300-1.27
Unit: mm
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2.25MAX
7.80.4
5.30.3
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PACKAGE OUTLINE(Continued)
SOP-20-375-1.27 Unit: mm
SSOP-20-300-0.65
Unit:mm
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PACKAGE OUTLINE(Continued)
SSOP-20-225-0.65 Unit:mm
MOS DEVICES OPERATE NOTES:
Electrostatic charges may exist in many things. Please take following preventive measures to prevent effectively the MOS electric circuit as a result of the damage which is caused by discharge: l l l l The operator must put on wrist strap which should be earthed to against electrostatic. Equipment cases should be earthed. All tools used during assembly, including soldering tools and solder baths, must be earthed. MOS devices should be packed in antistatic/conductive containers for transportation.
Disclaimer: * * Silan reserves the right to make changes to the information herein for the improvement of the design and performance without further notice! All semiconductor products malfunction or fail with some probability under special conditions. When using Silan products in system design or complete machine manufacturing, it is the responsibility of the buyer to comply with the safety standards strictly and take essential measures to avoid situations in which a malfunction or failure of such Silan products could cause loss of body injury or damage to property. * Silan will supply the best possible product for customers!
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